1. Field of the Invention
The present invention relates to an electrolytic processing apparatus and method, and more particularly to an electrolytic processing apparatus and method for filling a metal such as copper (Cu) or the like in fine interconnection patterns (recesses) formed in a semiconductor substrate.
2. Description of the Related Art
In recent years, instead of using aluminum or aluminum alloys as a material for forming interconnection circuits on a semiconductor substrate, there is an eminent movement towards using copper (Cu) that has a low electric resistivity and high electromigration endurance. Copper interconnects are generally formed by filling copper into fine recesses formed in the surface of a substrate. There are known various techniques for forming such copper interconnects, including CVD, sputtering, and plating. According to any such technique, a copper film is formed in the substantially entire surface of a substrate, followed by removal of unnecessary copper by performing chemical mechanical polishing (CMP).
FIGS. 22A through 22C illustrate, in sequence of process steps, an example of forming such a substrate W having copper interconnects. As shown in FIG. 22A, an insulating film 2, such as a silicon oxide film of SiO2 or a film of low-k material, is deposited on a conductive layer 1a in which electronic devices are formed, which is formed on a semiconductor base 1. A contact hole 3 and a trench 4 for interconnects are formed in the insulating film 2 by performing a lithography/etching technique. Thereafter, a barrier layer 5 of TaN or the like is formed on the entire surface, and a seed layer 7 as an electric supply layer for electroplating is formed on the barrier layer 5.
Then, as shown in FIG. 22B, copper plating is performed onto a surface of the substrate W to fill the contact hole 3 and the trench 4 with copper and, at the same time, deposit a copper film 6 on the insulating film 2. Thereafter, the copper film 6 and the barrier layer 5 on the insulating film 2 are removed by performing chemical mechanical polishing (CMP) so as to make the surface of the copper filled in the contact hole 3 and the trench 4 for interconnects and the surface of the insulating film 2 lie substantially on the same plane. Interconnects composed of the copper film 6 as shown in FIG. 22C are thus formed.
By the way, as shown in FIG. 23, when the copper film 6 is formed by performing plating on the surface of the substrate W in which a fine groove(s) 8 with a width d1, e.g., of the order of 0.1 μm, and a large groove(s) 9 with a width d2, e.g., of the order of 100 μm are present, the growth of plating is likely to be promoted at the portion above the fine groove 8 whereby the copper film 6 is raised at that portion, even when the effect of a plating solution or an additive contained in the plating solution is optimized, whereas the growth of plating with an adequately high leveling property cannot be made within the large groove 9. This results in a difference (a+b) in the level of the copper film 6 deposited on the substrate W, i.e. the height a of the raised portion above the fine groove 8 plus the depth b of the depressed portion above the large groove 9. Thus, in order to obtain the desired flat surface of substrate W with the fine groove 8 and the large groove 9 being fully filled with copper, it is necessary to provide the copper film 6 having a sufficiently large thickness beforehand, and remove by performing CMP the extra portion corresponding to the above difference (a+b) in the level.
This involves problems that the large thickness of the plated film requires a prolonged time for processing by CMP in order to polish away the large amount. Increasing the rate of CMP processing to avoid the prolongation of processing time can cause dishing in the large groove.
In order to solve these problems, it is necessary to make the thickness of a plated film as thin as possible, and reduce or eliminate the raised portions and recesses in the plated film even when fine grooves and large grooves are co-present in the surface of a substrate to thereby improve the flatness of the plated film. At present, however, when performing plating using, for example, a copper sulfate plating bath, it is not possible to simultaneously decrease the raised portions and decrease the recesses solely by the action of the plating solution or an additive. It is possible to reduce the raised portions by temporarily using a reverse voltage during plating or using a PR pulse power source as a plating power source. This method, however, is not effective in decreasing the recesses and, in addition, deteriorates the quality of the surface of the plated film.
Further, a chemical/mechanical/electrical polishing method, in which CMP processing and plating are carried out simultaneously, has been proposed. This method involves mechanical processing of the growing surface of plating, which includes an abnormal growth of plating, leading to a poor film quality.